1. Field of the Invention
The present invention relates generally to data transfers in systems, and in particular, relates to improving data transfer and bus efficiency by minimizing bus contention when a device writes data to memory.
2. Background Information
In computer systems, components are coupled to each other via one or more busses. A variety of components can be coupled to the bus, thereby providing intercommunication between all of the various components/devices. An example of a bus that is used for data transfer with a processor or for data transfer between a memory and another device is the peripheral component interconnect (PCI) bus.
In order to relieve a processor of the burden of controlling the movement of blocks of data inside of a computer, direct memory access (DMA) transfers are commonly used. With DMA transfers, data can be transferred from one memory location to another memory location, or from a memory location to an input/output (I/O) device (and vice versa), without having to go through the processor. Additional bus efficiency is achieved by allowing some of the devices connected to the PCI bus to be DMA masters.
When transferring data using DMA methods, scatter gather descriptors are often used. High performance I/O controllers, such as gigabit Ethernet media access control (MAC) network controllers, are typically scatter gather descriptor-based bus-mastering devices that allow a computer to communicate with a network. The scatter gather descriptors are used to provide address and control information about data buffers (or xe2x80x9cscatter gather elementsxe2x80x9d) in memory that the controller needs to read or write for I/O operations. For example, the descriptors provide information such as the memory location from where bytes of data are to be moved, the address to where the bytes should go, the number of bytes to move, etc.
To write data into data buffers of a memory using DMA transfers, such as when incoming data received by the controller is to be written into memory, the controller needs to be informed of available data buffer locations in memory, so that the controller can send the data to these locations. A driver for the controller generally uses scatter gather descriptors to inform the controller of these available data buffer locations. The driver first allocates data buffers in memory and inserts information into descriptors that point at these available data buffers. Next, the driver writes to a command register of the controller to inform the controller that the descriptor(s) are ready to be processed/read. The controller then DMA transfers the descriptor(s) from memory to a first-in-first-out (FIFO) buffer, for example, so that the controller can obtain the data buffer""s information (e.g., identify the data buffer""s memory location, length, etc.). After the controller has processed the descriptor(s) to obtain this information, the controller knows the locations of available data buffers in memory and can DMA transfer the received contents/data (e.g., frames) to the data buffer(s) referred to by the descriptor(s).
As the controller receives more incoming data, the controller needs more bus bandwidth and consumes more data buffers. Therefore, after data in data buffers is processed, such data buffers are overwritten with new data. In other words, the data buffers are repeatedly xe2x80x9creplenishedxe2x80x9d so that they can be used by the controller.
The driver needs to inform the controller of these replenished or xe2x80x9creplacementxe2x80x9d data buffers to prevent overruns. That is, the driver generally informs the controller that more data buffer(s) are ready by writing to a command register of the controller. These writes to the command register are typically slave accesses to the controller performed by a bus bridge. In order for the bus bridge to perform these writes, the bus bridge removes control of the bus from the controller. In cases where the controller is under heavy load (e.g., receiving a large number of frames), losing control of the bus can cause overruns. Overruns occur if data continues to come to the controller (e.g., from the network) and the controller cannot move the data to system memory with sufficient speed, thereby causing on-chip buffers in the controller to fill beyond capacity. This can result in lost data.
Therefore, it is evident that when high-speed performance by a controller is desired, multiple problems occur. As data throughput increases, available data buffers are consumed more quickly. These data buffers must be replenished, but the act of replacing them, including the act of informing the controller of the availability of these data buffers, can reduce bus bandwidth to the controller when the controller needs the bus bandwidth the most.